From 321111774ce013b35641fe6d0e03e693974b4a28 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 16 Aug 2017 11:40:03 -0700 Subject: soc/intel/cannonlake: Add SPI flash controller driver Add SPI driver code for the SPI flash controller, including both fast_spi and generic_spi. Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21052 Tested-by: build bot (Jenkins) Reviewed-by: Pratikkumar Prajapati Reviewed-by: Aaron Durbin --- src/soc/intel/cannonlake/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 311cfb8a8c..1b6759cd9b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -11,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET @@ -29,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_RTC @@ -38,6 +41,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT select SOC_INTEL_COMMON_RESET select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE @@ -78,6 +82,11 @@ config CPU_BCLK_MHZ int default 100 + +config SOC_INTEL_COMMON_BLOCK_GSPI_MAX + int + default 3 + # Clock divider parameters for 115200 baud rate config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL hex -- cgit v1.2.3