From 031020e431f8d013108957b856da5ff5c7c596f3 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Fri, 15 Dec 2017 12:58:07 -0800 Subject: soc/intel/cannonlake: Correct PMC/GPIO routing information PMC and GPIO DWx definition is not identical, hence update that to correct information. For cannonlake lp PCH, GPIO group C, group E and group GPD is different for PMC GPIO_CFG and GPIO MISCCFG. Also add function call to set up GPE routing in bootblock stage. TEST=Boot up into OS, and manually check PMC GPE status Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/22908 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Nick Vaccaro --- src/soc/intel/cannonlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/cannonlake/Kconfig') diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 51cd23fc47..a19a371374 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -165,7 +165,7 @@ config VBOOT config C_ENV_BOOTBLOCK_SIZE hex - default 0x4000 + default 0x8000 config STACK_SIZE hex -- cgit v1.2.3