From df128a55b183d3d7a6d7ae986f33abffac50f371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Sep 2019 18:35:37 +0300 Subject: intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/pcie.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/broadwell') diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bdaced2edd..36523411c3 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -604,10 +604,10 @@ static void pch_pcie_init(struct device *dev) /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); -- cgit v1.2.3