From 4658a98a63b36b376de1de228c293b5ef6dbb132 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 20 Sep 2018 08:46:35 +0200 Subject: soc/broadwell: Don't use device_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use of device_t is deprecated. Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28692 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/soc/intel/broadwell/xhci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/broadwell/xhci.c') diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 75a63cfca3..8b4c7b1b5e 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -25,7 +25,7 @@ #include #ifdef __SMM__ -static u8 *usb_xhci_mem_base(device_t dev) +static u8 *usb_xhci_mem_base(pci_devfn_t dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -36,7 +36,7 @@ static u8 *usb_xhci_mem_base(device_t dev) return (u8 *)(mem_base & ~0xf); } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(pci_devfn_t dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -69,7 +69,7 @@ static void usb_xhci_reset_port_usb3(u8 *mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(pci_devfn_t dev, int all) { u32 status, port_disabled; int timeout, port; @@ -140,7 +140,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ) { u16 reg16; u32 reg32; -- cgit v1.2.3