From 42d1660e4e85c472f55a4d999239634c19e0996b Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 4 Jul 2018 16:32:21 -0500 Subject: soc/intel/broadwell: implement RMRR ACPI table Modeled after Skylake implementation; uses duplicated intel common SA functions to get RMRR addresses Test: build/boot purism/librem13v1, observe IOMMU fully functional with intel_iommu=on kernel parameter Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/30234 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/systemagent.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/soc/intel/broadwell/systemagent.c') diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 80139795d6..e0d8b765a4 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -36,6 +36,18 @@ u8 systemagent_revision(void) return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); } +uintptr_t sa_get_tolud_base(void) +{ + /* Bit 0 is lock bit, not part of address */ + return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1; +} + +uintptr_t sa_get_gsm_base(void) +{ + /* Bit 0 is lock bit, not part of address */ + return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1; +} + static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { -- cgit v1.2.3