From b887adf7a56f2877c41e808002f30841a6679eb6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:42:34 +0200 Subject: soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/serialio.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/soc/intel/broadwell/serialio.c') diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index a4922f7d73..9e6cf32a9c 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -160,14 +160,11 @@ static void serialio_init(struct device *dev) config_t *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; - u32 reg32; printk(BIOS_DEBUG, "Initializing Serial IO device\n"); /* Ensure memory and bus master are enabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); -- cgit v1.2.3