From 55228ba4b41e820efea71a75c649a6dd29cc76d5 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 25 Aug 2014 10:14:08 -0700 Subject: broadwell: Changes from 2.2.0 ref code - The SATA CAP register setup was moved outside the refcode blob we run so it needs to be set up by coreboot again... - Slight tweak to fast ramp voltage for broadwell CPU BUG=chrome-os-partner:25491 BRANCH=None TEST=Build and boot on samus Original-Change-Id: I7bdc0811ad8f28ab0912972036dca59d229b0173 Original-CSigned-off-by: Duncan Laurie Original-CReviewed-on: https://chromium-review.googlesource.com/214024 Original-CReviewed-by: Aaron Durbin (cherry picked from commit 5d166a0c4d206eaa885ecebaa0c3cefefdc59280) Signed-off-by: Marc Jones Change-Id: Id58d3bee5e713139edf6e8fda8cdf4c48ba95bd1 Reviewed-on: http://review.coreboot.org/8964 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/sata.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/soc/intel/broadwell/sata.c') diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e9e0810de1..0e2516185a 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -92,6 +92,13 @@ static void sata_init(struct device *dev) abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); printk(BIOS_DEBUG, "ABAR: %p\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ + write32(abar + 0x00, reg32); + /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ -- cgit v1.2.3