From 46134728402601abc85a6a9ee01d37f0d50cc705 Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 28 Aug 2014 17:05:06 -0700 Subject: broadwell: Fix some errors in selftest 1. Fixed some errors in selftest compare to reference. 2. Some WA steps for xhci in sleep trap is only for lpt. BUG=chrome-os-partner:28234 TEST=compile ok, run selftest on auron to verify boot to OS BRANCH=None Signed-off-by: Kane Chen Original-Change-Id: Iaccb087581d5f51453614246bf80132fcb414131 Original-Reviewed-on: https://chromium-review.googlesource.com/215646 Original-Reviewed-by: Duncan Laurie Original-Commit-Queue: Kane Chen Original-Tested-by: Kane Chen (cherry picked from commit 97761b4ad3073fff89aabce3ef4f763383ca5cad) Signed-off-by: Marc Jones Change-Id: I2b1d5be4f8a13eb00009a36a199520cd35a67abf Reviewed-on: http://review.coreboot.org/8971 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/broadwell/sata.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/broadwell/sata.c') diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 0e2516185a..6859ffce37 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -209,6 +209,10 @@ static void sata_init(struct device *dev) reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); + reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 29; + pci_write_config32(dev, 0x98, reg32); + /* Register Lock */ reg32 = pci_read_config32(dev, 0x9c); reg32 |= (1 << 31); -- cgit v1.2.3