From 446fb8e45ef2d555579e7659c1c0a91bb8ff3d78 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 8 Aug 2014 09:59:43 -0700 Subject: broadwell: Misc updates from 2.1.0 ref code - ADSP IRQ should be exclusive - HDA should write reg 0x43 even if disabled - A few clock gating tweaks based on ref code changes - Move SATA clock gating to sata.c where SIR changes are done - Add support for enabling Deep SX in AC/DC modes - CLKREQ VR Idle for enabled PCIE ports BUG=chrome-os-partner:28234 BRANCH=None TEST=build and boot on samus Original-Change-Id: Icece58e32b7a5d2b359debd5516a230cae3fd48c Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/211611 Original-Reviewed-by: Aaron Durbin (cherry picked from commit c0e22ba043ed96bdddca4989b2f29d0e989f6fef) Signed-off-by: Marc Jones Change-Id: If5f5e1666aa9660e31305ee6369f2febf6757b99 Reviewed-on: http://review.coreboot.org/8952 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/sata.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/broadwell/sata.c') diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 13b4fe09bf..3b9c1d81f7 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -211,9 +211,10 @@ static void sata_init(struct device *dev) sir_write(dev, 0x70, 0x3f00bf1f); sir_write(dev, 0x54, 0xcf000f0f); sir_write(dev, 0x58, 0x00190000); + RCBA32_AND_OR(0x333c, 0xffcfffff, 0x00c00000); reg32 = pci_read_config32(dev, 0x300); - reg32 |= (1 << 17) | (1 << 16); + reg32 |= (1 << 17) | (1 << 16) | (1 << 19); reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); } -- cgit v1.2.3