From 5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 22 Dec 2018 16:02:25 +0100 Subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/30383 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/romstage/Makefile.inc | 2 -- src/soc/intel/broadwell/romstage/romstage.c | 4 +--- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'src/soc/intel/broadwell/romstage') diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index cc0a05124f..ea17d67061 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 25c47c62c2..54434a3153 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -67,9 +67,7 @@ void platform_enter_postcar(void) /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(unsigned long bist) { - struct romstage_params rp = { - .bist = bist, - }; + struct romstage_params rp = { 0 }; post_code(0x30); -- cgit v1.2.3