From cadc70f7974db25144381b3ea26d4b660233f4dd Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sun, 12 May 2019 13:44:22 +0200
Subject: soc/intel/broadwell: Move GPIO init to a common place

This also links the gpio configuration instead of including it as a
header.

Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
---
 src/soc/intel/broadwell/romstage/romstage.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/broadwell/romstage/romstage.c')

diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 2531665f1f..7847829ac6 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -27,6 +27,7 @@
 #include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
+#include <soc/gpio.h>
 #include <soc/me.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
@@ -100,6 +101,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
 	/* Set CPU frequency to maximum */
 	set_max_freq();
 
+	/* Initialize GPIOs */
+	init_gpios(mainboard_gpio_config);
+
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&rp);
 
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