From b887adf7a56f2877c41e808002f30841a6679eb6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 10:42:34 +0200 Subject: soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/pcie.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'src/soc/intel/broadwell/pcie.c') diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index f81f0429f2..d506057d61 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -574,19 +574,14 @@ static void pch_pcie_early(struct device *dev) static void pch_pcie_init(struct device *dev) { u16 reg16; - u32 reg32; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); @@ -597,6 +592,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); -- cgit v1.2.3