From f58e53601669133b1f23eb2a580171075054418f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 8 Sep 2021 13:30:17 +0200 Subject: lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/pcie.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/broadwell/pch') diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index ef03eee4d3..966a25d661 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -452,17 +452,17 @@ static void pch_pcie_early(struct device *dev) break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspond to - * Root Ports 4:1. + * Bit 28 of b0d28f4 0x32c register corresponds to + * Root Port 5. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspond to - * Root Ports 4:1. + * Bit 29 of b0d28f5 0x32c register corresponds to + * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); + do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); break; } -- cgit v1.2.3