From 64c6a746ac78a207703d18b806cb0baa223ebbf5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 28 Jan 2021 15:09:39 +0100 Subject: soc/intel/broadwell: Use southbridge common RCBA Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I94953bed3f331848271464bee829f8209167f150 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50041 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/pch/acpi/pch.asl | 2 +- src/soc/intel/broadwell/pch/bootblock.c | 4 ++-- src/soc/intel/broadwell/pch/lpc.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/soc/intel/broadwell/pch') diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index b7d6838f51..0e90c957d4 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -13,7 +13,7 @@ Scope (\) } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index 7f6d0d52d9..d00a43173e 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -13,7 +13,7 @@ static void map_rcba(void) { - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); } static void enable_port80_on_lpc(void) @@ -48,7 +48,7 @@ static void set_spi_speed(void) static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, CONFIG_FIXED_RCBA_MMIO_BASE | 1); pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 84b8d00938..873e57e12a 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -491,10 +491,10 @@ static void pch_lpc_add_mmio_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* RCBA */ - if (default_decode_base > RCBA_BASE_ADDRESS) { + if (default_decode_base > CONFIG_FIXED_RCBA_MMIO_BASE) { res = new_resource(dev, RCBA); - res->base = RCBA_BASE_ADDRESS; - res->size = 16 * 1024; + res->base = CONFIG_FIXED_RCBA_MMIO_BASE; + res->size = CONFIG_RCBA_LENGTH; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; } -- cgit v1.2.3