From 0a45b40fb2fc2e0a7bf64e1721d0b60748949e4d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 26 Jan 2021 19:28:28 +0100 Subject: soc/intel/broadwell: Move `ramstage.c` to PCH scope The remaining code in this file is PCH-specific. Change-Id: I0e4924e680db9c25aeb222bdd478b3282a77b34f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49946 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/pch/Makefile.inc | 1 + src/soc/intel/broadwell/pch/ramstage.c | 74 ++++++++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 src/soc/intel/broadwell/pch/ramstage.c (limited to 'src/soc/intel/broadwell/pch') diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 119534fccd..1a1965a822 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += pmutil.c smm-y += pmutil.c verstage-y += pmutil.c romstage-y += power_state.c +ramstage-y += ramstage.c ramstage-y += sata.c ramstage-y += serialio.c ramstage-y += smbus.c diff --git a/src/soc/intel/broadwell/pch/ramstage.c b/src/soc/intel/broadwell/pch/ramstage.c new file mode 100644 index 0000000000..a75bd36c99 --- /dev/null +++ b/src/soc/intel/broadwell/pch/ramstage.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ +static void pm_fill_gnvs(struct global_nvs *gnvs, const struct chipset_power_state *ps) +{ + uint16_t pm1; + int gpe_reg; + + pm1 = ps->pm1_sts & ps->pm1_en; + + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + gnvs->gpei = -1; + for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { + u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; + int start = gpe_reg * GPE0_REG_SIZE; + int end = start + GPE0_REG_SIZE; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + gnvs->pm1i, gnvs->gpei); +} + +static void acpi_save_wake_source(void *unused) +{ + const struct chipset_power_state *ps; + struct global_nvs *gnvs = acpi_get_gnvs(); + if (!gnvs) + return; + + if (acpi_pm_state_for_wake(&ps) < 0) + return; + + pm_fill_gnvs(gnvs, ps); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); -- cgit v1.2.3