From 040f3be59e592311bf7d8f658b2cca1189d62f2c Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 25 Oct 2020 14:01:06 +0100
Subject: soc/intel/broadwell: Include EC and IRQ links ACPI early
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Other southbridges such as Lynx Point do it. This eases merging later.

Change-Id: I10196bbc44ce859c2747755845378351f45944ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/broadwell/pch/acpi/lpc.asl | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/soc/intel/broadwell/pch/acpi')

diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index 01e1bebaf9..0af85e62cc 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -31,6 +31,10 @@ Device (LPCB)
 		IOD1,	8,
 	}
 
+	#include <southbridge/intel/common/acpi/irqlinks.asl>
+
+	#include "acpi/ec.asl"
+
 	Device (DMAC)	// DMA Controller
 	{
 		Name (_HID, EISAID("PNP0200"))
@@ -180,7 +184,5 @@ Device (LPCB)
 	}
 
 	#include "gpio.asl"
-	#include <southbridge/intel/common/acpi/irqlinks.asl>
-	#include "acpi/ec.asl"
 	#include "acpi/superio.asl"
 }
-- 
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