From 81dc352032cacb309ed9335f394969d847820511 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 8 Apr 2023 09:43:56 +0300 Subject: intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change IRQ #0 to GSI #2 override to positive edge trigger from the bus ISA default (positive edge). Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/intel/broadwell/pch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/broadwell/pch/Kconfig') diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig index 63f0439e6a..bd1bea5f20 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/soc/intel/broadwell/pch/Kconfig @@ -4,6 +4,7 @@ config INTEL_LYNXPOINT_LP config PCH_SPECIFIC_OPTIONS def_bool y + select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS @@ -17,7 +18,6 @@ config PCH_SPECIFIC_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_LYNXPOINT_LP select RTC - select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET select SOUTHBRIDGE_INTEL_COMMON_RTC -- cgit v1.2.3