From 8f09688d23e326b053dac9a1dfc167a1ddf6a5a1 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 15 Aug 2019 11:29:15 +0300 Subject: intel/broadwell: Use smm_subregion() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/memmap.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/broadwell/memmap.c') diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 7c53fa6468..f4a9d0ed24 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -16,12 +16,12 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include #include #include #include -#include #include static uintptr_t dpr_region_start(void) @@ -46,14 +46,13 @@ void *cbmem_top(void) return (void *) dpr_region_start(); } -void stage_cache_external_region(void **base, size_t *size) +void smm_region(uintptr_t *start, size_t *size) { - /* The ramstage cache lives in the TSEG region. - * The top of RAM is defined to be the TSEG base address. */ - u32 offset = smm_region_size(); - offset -= CONFIG_IED_REGION_SIZE; - offset -= CONFIG_SMM_RESERVED_SIZE; - - *base = (void *)(cbmem_top() + offset); - *size = CONFIG_SMM_RESERVED_SIZE; + uintptr_t tseg = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); + uintptr_t bgsm = pci_read_config32(PCI_DEV(0, 0, 0), BGSM); + + tseg = ALIGN_DOWN(tseg, 1 * MiB); + bgsm = ALIGN_DOWN(bgsm, 1 * MiB); + *start = tseg; + *size = bgsm - tseg; } -- cgit v1.2.3