From 3c1e986119cdfece27e5bf953576fa01882bb773 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 13 Oct 2019 22:54:53 +0200 Subject: soc/intel/broadwell: Use common sb code for SPI lockdown configuration Change-Id: I5a8239f4e9e1f9728074ff5452c95d3138965d82 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36005 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/finalize.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/broadwell/finalize.c') diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 10ba1d7c15..1c5fdb8885 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -27,6 +27,7 @@ #include #include #include +#include const struct reg_script system_agent_finalize_script[] = { REG_PCI_OR16(0x50, 1 << 0), /* GGC */ @@ -57,16 +58,6 @@ const struct reg_script system_agent_finalize_script[] = { const struct reg_script pch_finalize_script[] = { #if !CONFIG(SPI_CONSOLE) - /* Set SPI opcode menu */ - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP, - SPI_OPPREFIX), - REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE, - SPI_OPTYPE), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + - SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER), - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + - SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER), - /* Lock SPIBAR */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, SPIBAR_HSFS_FLOCKDN), @@ -101,6 +92,8 @@ static void broadwell_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); reg_script_run_on_dev(sa_dev, system_agent_finalize_script); + + spi_finalize_ops(); reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); /* Lock */ -- cgit v1.2.3