From c715dc80f92f5cf1d29b53f2b2166e2a4f4b3dc4 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 31 Jan 2021 00:33:04 +0100 Subject: soc/intel/broadwell: Use common {DMI,EP,MCH}BAR accessors Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I04dbeade44d480301c9f7d336449bc54e56cb7bc Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/50169 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/broadwell/early_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/broadwell/early_init.c') diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index 6bf7ba7a59..6c347f3380 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,9 +11,9 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(SA_DEV_ROOT, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(SA_DEV_ROOT, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(SA_DEV_ROOT, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; -- cgit v1.2.3