From 1fad694953add0af54721647e5be360045987142 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 29 Sep 2014 08:51:45 -0700 Subject: broadwell: Add support for ACPI \_GPE._SWS In order to report the GPE that woke the system to the kernel coreboot needs to keep track of the first GPE wake source and save it in NVS so it can be returned in \_GPE._SWS method. This is similar to the saving of PM1 status but needs to go through all the GPE0_STS registers and check for enabled and triggered events. A bit of cleanup is done for areas that were touched: - platform.asl was not formatted correctly BUG=chrome-os-partner:8127 BRANCH=samus,auron TEST=manual: - suspend/resume and wake from EC event like keyboard: ACPI _SWS is PM1 Index -1 GPE Index 112 ("special" GPIO27) - suspend/resume and wake from RTC event: ACPI _SWS is PM1 Index 10 GPE Index -1 (RTC) - suspend/resume and wake from power button: ACPI _SWS is PM1 Index 8 GPE Index -1 - suspend/resume and wake from touchpad: ACPI _SWS is PM1 Index -1 GPE Index 13 - suspend/resume and wake from WLAN: ACPI _SWS is PM1 Index -1 GPE Index 10 Change-Id: I574f8cd83c8bb42f420e1a00e71a23aa23195f53 Signed-off-by: Stefan Reinauer Original-Commit-Id: d4e06c7dfc73f2952ce8f81263e316980aa9760f Original-Change-Id: I9bfbbe4385f2acc2a50f41ae321b4bae262b7078 Original-Signed-off-by: Duncan Laurie Original-Reviewed-on: https://chromium-review.googlesource.com/220324 Original-Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/9460 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/broadwell/acpi/globalnvs.asl | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/broadwell/acpi/globalnvs.asl') diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/acpi/globalnvs.asl index d8b75ac8c1..4ba384a4af 100644 --- a/src/soc/intel/broadwell/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/acpi/globalnvs.asl @@ -62,6 +62,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) CMEM, 32, // 0x19 - 0x1c - CBMEM TOC CBMC, 32, // 0x1d - 0x20 - Coreboot Memory Console PM1I, 32, // 0x21 - 0x24 - PM1 wake status bit + GPEI, 32, // 0x25 - 0x28 - GPE wake status bit /* ChromeOS specific */ Offset (0x100), -- cgit v1.2.3