From a6354a1acadc7825364c6a6e7fd3b24a405a62a1 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Fri, 26 Dec 2014 22:11:14 -0700
Subject: broadwell: Preparations for building

Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.

- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic

Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
---
 src/soc/intel/broadwell/Makefile.inc | 33 ++++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

(limited to 'src/soc/intel/broadwell/Makefile.inc')

diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 1de2a016f2..43be95ecf4 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += acpi.c
 ramstage-y += adsp.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
-ramstage-y += elog.c
+ramstage-$(CONFIG_ELOG) += elog.c
 ramstage-y += finalize.c
 ramstage-y += gpio.c
 romstage-y += gpio.c
@@ -69,20 +69,38 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
-INCLUDES += -Isrc/soc/intel/broadwell/
+CPPFLAGS_common += -Isrc/soc/intel/broadwell/
 
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
-INTERMEDIATE := pch_add_me
+INTERMEDIATE := broadwell_add_me
 
-pch_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
+IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
+		$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
+		$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
+else
+IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
+endif
+
+broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
+ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
+	printf "\n** WARNING **\n"
+	printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
+	printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
+	printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
+	printf "    IFDFAKE    Building a fake Intel Firmware Descriptor\n"
+	$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
+endif
 	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
+	dd if=$(IFD_BIN_PATH) \
 		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+ifeq ($(CONFIG_HAVE_ME_BIN),y)
 	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
 	$(objutil)/ifdtool/ifdtool \
-		-i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
+		-i ME:$(CONFIG_ME_BIN_PATH) \
 		$(obj)/coreboot.pre
 	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
 ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
@@ -94,8 +112,9 @@ else
 	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
 	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
 endif
+endif
 
-PHONY += pch_add_me
+PHONY += broadwell_add_me
 
 # If an MRC file is an ELF file determine the entry address and first loadable
 # section offset in the file. Subtract the offset from the entry address to
-- 
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