From b71d9b8a0f02d5f458620cb21cdfe7799b1faf84 Mon Sep 17 00:00:00 2001 From: Kenji Chen Date: Fri, 10 Oct 2014 03:08:15 +0800 Subject: Broadwell: Select PCIE_L1_SUB_STATE and apply Broadwell settings. Signed-off-by: Stefan Reinauer BUG=chrome-os-partner:31424 TEST=Build an image and confirm the settings are correctly applied to registers for PCIe L1 Sub-State feature enabling. Original-Commit-Id: b94c8c715febe3a04bfdf52f7b69d73ece0f6faf Original-Signed-off-by: Kenji Chen Original-Change-Id: I07ce6eea648b1b37d606f5529edad184e3de70ac Original-Reviewed-on: https://chromium-review.googlesource.com/222599 Original-Reviewed-by: Duncan Laurie Change-Id: I07336599797c09bf23e5b15059d6ad812fdc7c61 Reviewed-on: http://review.coreboot.org/9223 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/soc/intel/broadwell/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/broadwell/Kconfig') diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index c14766343d..2e70f45eea 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE select SMM_MODULES select SMM_TSEG select SMP -- cgit v1.2.3