From 2bad1e7f491ea9347899498d7d8dde4e1dd9b6d4 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 26 Jul 2016 14:03:31 +0300 Subject: intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/Kconfig | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/soc/intel/broadwell/Kconfig') diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 517fd21ee8..29b5bfe6fa 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -106,13 +106,6 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. -config DCACHE_RAM_ROMSTAGE_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage from the data cache - during pre-ram ROM stage execution. - config HAVE_MRC bool "Add a Memory Reference Code binary" help -- cgit v1.2.3