From f01a15952adb903fed169dbcef1e4a33cc88ba3f Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 31 Oct 2018 10:07:11 +0100 Subject: src/soc/intel/braswell/acpi/lpc.asl: Add ACPI and GPIO bases ACPI and GPIO base are used by LPC controller, but not reserved. Both bases are added to the LPC device resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/29288 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/intel/braswell/acpi/lpc.asl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index ce83009a1b..067b05f6de 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -106,6 +106,10 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, + 0x1, ACPI_BASE_SIZE) /* ACPI Base */ + IO (Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, + 0x1, 0xff) /* GPIO Base */ }) Method (_CRS, 0, NotSerialized) -- cgit v1.2.3