From ec562161cd2265c924482835fd2ab32c13ba587e Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 4 May 2019 17:17:40 +0200 Subject: soc/intel/bsw: Move memory init values into `romstage.h` `chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592 Reviewed-by: Patrick Georgi Reviewed-by: Matt DeVillier Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/chip.h | 3 --- src/soc/intel/braswell/include/soc/romstage.h | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index bb06dd595a..5a00328f4d 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,9 +32,6 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 -#define MEM_DDR3 0 -#define MEM_LPDDR3 1 - enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 8fa9c8a713..2512430f75 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -34,4 +34,8 @@ void set_max_freq(void); void program_base_addresses(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); +/* Values for FSP's PcdMemoryTypeEnable */ +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + #endif /* _SOC_ROMSTAGE_H_ */ -- cgit v1.2.3