From ad8669ef30743489909cd07be7759b29cf1dbe30 Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Tue, 21 Mar 2017 22:34:01 -0700 Subject: soc/intel/braswell: Populate NVS SCC BAR1 Cherry-pick from Chromium commit f92d7be. This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put SD controller in D3 Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9 Original-Signed-off-by: Hannah Williams Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Duncan Laurie Original-Tested-by: Aseda Aboagye Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/21172 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/scc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 3172b73247..6538c5cda0 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -42,7 +42,10 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + gnvs->dev.scc_bar0[nvs_index] = bar->base; + bar = find_resource(dev, PCI_BASE_ADDRESS_2); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = bar->base; /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; -- cgit v1.2.3