From 76cedd2c292352d7dbd45fab70ec272e476d0910 Mon Sep 17 00:00:00 2001
From: Furquan Shaikh <furquan@google.com>
Date: Sat, 2 May 2020 10:24:23 -0700
Subject: acpi: Move ACPI table support out of arch/x86 (3/5)

This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/soc/intel/braswell/acpi.c             | 4 ++--
 src/soc/intel/braswell/elog.c             | 2 +-
 src/soc/intel/braswell/include/soc/acpi.h | 2 +-
 src/soc/intel/braswell/include/soc/pm.h   | 2 +-
 src/soc/intel/braswell/northcluster.c     | 2 +-
 src/soc/intel/braswell/pmutil.c           | 2 +-
 src/soc/intel/braswell/ramstage.c         | 2 +-
 src/soc/intel/braswell/southcluster.c     | 2 +-
 8 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/soc/intel/braswell')

diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 1c9d6b3e9b..0954e58c95 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <device/mmio.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c
index 615117c613..6f35d064dd 100644
--- a/src/soc/intel/braswell/elog.c
+++ b/src/soc/intel/braswell/elog.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <device/device.h>
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 997b7e920c..ef476456af 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -4,7 +4,7 @@
 #ifndef _SOC_ACPI_H_
 #define _SOC_ACPI_H_
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <soc/nvs.h>
 
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h
index f3397aaa4b..2ca2b5d1b1 100644
--- a/src/soc/intel/braswell/include/soc/pm.h
+++ b/src/soc/intel/braswell/include/soc/pm.h
@@ -4,7 +4,7 @@
 #ifndef _SOC_PM_H_
 #define _SOC_PM_H_
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 
 #define IOCOM1		0x3f8
 
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index 3222faf814..5dca249e0b 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <cbmem.h>
 #include <cpu/x86/smm.h>
 #include <device/device.h>
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 1ca8bdaccc..aaa6e480f9 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* This file is part of the coreboot project. */
 
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <arch/io.h>
 #include <assert.h>
 #include <bootmode.h>
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index e2d9a3b101..5d6ecab8c4 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -2,7 +2,7 @@
 /* This file is part of the coreboot project. */
 
 #include <arch/cpu.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 9b5784c2b5..14c42022dc 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -4,7 +4,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 #include <arch/ioapic.h>
 #include <bootstate.h>
 #include "chip.h"
-- 
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