From 5a55a455cd03000aeb6a0b085e0779f99b85e26c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 24 Jun 2021 20:49:05 +0300 Subject: soc/intel/baytrail,braswell: Do resource transition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/northcluster.c | 2 +- src/soc/intel/braswell/southcluster.c | 30 ++++++++++++------------------ 2 files changed, 13 insertions(+), 19 deletions(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index a39b6db030..6f82581dde 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -99,7 +99,7 @@ static void nc_read_resources(struct device *dev) /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource_kb(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + mmio_range(dev, BUNIT_MMCONF_REG, mmconf, CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB); /* 0 -> 0xa0000 */ base_k = RES_IN_KiB(0); diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 0f762fcb8c..a0df97cdf7 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -45,26 +45,20 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode) } } -static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr, - unsigned long size) -{ - mmio_resource_kb(dev, i, addr >> 10, size >> 10); -} - static void sc_add_mmio_resources(struct device *dev) { - add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); - add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); - add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); - add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); - add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); - add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); - add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); - add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); - add_mmio_resource(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1, - (CONFIG_COREBOOT_ROMSIZE_KB * KiB)); /* BIOS ROM */ - - add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ + mmio_range(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); + mmio_range(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); + mmio_range(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); + mmio_range(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); + mmio_range(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); + mmio_range(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); + mmio_range(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); + mmio_range(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); + mmio_range(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1, + CONFIG_COREBOOT_ROMSIZE_KB * KiB); /* BIOS ROM */ + + mmio_range(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */ } /* Default IO range claimed by the LPC device. The upper bound is exclusive. */ -- cgit v1.2.3