From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 1 Oct 2018 08:47:51 +0200 Subject: src: Move common IA-32 MSRs to Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth Reviewed-by: Lijian Zhao Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/cpu.c | 2 +- src/soc/intel/braswell/include/soc/msr.h | 4 ---- src/soc/intel/braswell/ramstage.c | 2 +- src/soc/intel/braswell/tsc_freq.c | 10 +++++----- 4 files changed, 7 insertions(+), 11 deletions(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 6ed12afa5f..27903e86e0 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -175,7 +175,7 @@ static void per_cpu_smm_trigger(void) msr_t msr_value; /* Need to make sure that all cores have microcode loaded. */ - msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + msr_value = rdmsr(IA32_BIOS_SIGN_ID); if (msr_value.hi == 0) intel_microcode_load_unlocked(pattrs->microcode_patch); diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 1a79b2faf5..6137820e9f 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -17,8 +17,6 @@ #ifndef _SOC_MSR_H_ #define _SOC_MSR_H_ -#define MSR_IA32_PLATFORM_ID 0x17 -#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PKG_CST_CONFIG_CONTROL 0xe2 @@ -26,8 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 20c09d5d52..a12db8034d 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -112,7 +112,7 @@ static void fill_in_pattrs(void) stepping_str[attrs->stepping]); } - fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID); fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007c66..72dbca5af9 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ void set_max_freq(void) msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of @@ -91,7 +91,7 @@ void set_max_freq(void) perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ -- cgit v1.2.3