From 2bad1e7f491ea9347899498d7d8dde4e1dd9b6d4 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 26 Jul 2016 14:03:31 +0300 Subject: intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not referenced in code. Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17268 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/Kconfig | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/braswell') diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b587988532..ddd7051ec7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -75,9 +75,9 @@ config SMM_RESERVED_SIZE # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE -# | Stack |\ -# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE -# | v |/ +# | Stack | +# | | | +# | v | # +-------------+ # | ^ | # | | | @@ -97,13 +97,6 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config DCACHE_RAM_ROMSTAGE_STACK_SIZE - hex - default 0x800 - help - The amount of anticipated stack usage from the data cache - during pre-ram ROM stage execution. - config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n -- cgit v1.2.3