From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 1 Oct 2018 08:47:51 +0200 Subject: src: Move common IA-32 MSRs to Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth Reviewed-by: Lijian Zhao Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/tsc_freq.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/braswell/tsc_freq.c') diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007c66..72dbca5af9 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ void set_max_freq(void) msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of @@ -91,7 +91,7 @@ void set_max_freq(void) perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ -- cgit v1.2.3