From bd5233eb3dbe2a7e3a0369ef13d4851062c347bd Mon Sep 17 00:00:00 2001
From: Frans Hendriks <fhendriks@eltan.com>
Date: Wed, 5 Dec 2018 15:24:48 +0100
Subject: src/soc/intel/braswell/southcluster.c: Config i8254 timer
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ISA timer is not configured.
Add call setup_i8254().

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
---
 src/soc/intel/braswell/southcluster.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/soc/intel/braswell/southcluster.c')

diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 0c88004323..6ea2ea9aae 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -4,6 +4,7 @@
  * Copyright (C) 2008-2009 coresystems GmbH
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +26,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <pc80/i8254.h>
 #include <romstage_handoff.h>
 #include <soc/acpi.h>
 #include <soc/iomap.h>
@@ -182,6 +184,8 @@ static void sc_init(struct device *dev)
 			read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 	}
 
+	/* Initialize i8254 timers */
+	setup_i8254();
 }
 
 /*
-- 
cgit v1.2.3