From 392d69957038b26ce1de5c3a88bb0828fec4c0d4 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 1 Nov 2018 14:02:57 +0100 Subject: src/soc/intel/braswell/romstage/romstage.c: Perform RTC init in romstage soc_rtc_init() is executed in ramstage The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC init from ramstage to romstage. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/29397 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/southcluster.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/soc/intel/braswell/southcluster.c') diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index ca87d63aa0..dd0c78e59a 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -149,12 +148,6 @@ static void sc_read_resources(struct device *dev) sc_add_io_resources(dev); } -static void sc_rtc_init(void) -{ - printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); - cmos_init(rtc_failure()); -} - static void sc_init(struct device *dev) { int i; @@ -181,8 +174,6 @@ static void sc_init(struct device *dev) /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); - sc_rtc_init(); - if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); write32(gen_pmcon1, -- cgit v1.2.3