From 863853cd2d8e01db2045e73d96c502e4ecba8ad1 Mon Sep 17 00:00:00 2001
From: Frans Hendriks <fhendriks@eltan.com>
Date: Tue, 18 Jun 2019 12:18:55 +0200
Subject: soc/intel/braswell/smbus.c: Add support for i2c mode block write
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Intel Braswell supports i2c block write using SMBus controller.

smbus_i2c_block_write() is added to configure SMBus controller in i2c
mode before calling do_i2c_block_write().

Add smbus.c to ramstage.

BUG=N/A
TEST=Verify LCD display is working on Facebook FBG-1701

Change-Id: I50c1a03f624b3ab3b987d4f3b1d15dac4374e48a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/soc/intel/braswell/smbus.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'src/soc/intel/braswell/smbus.c')

diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c
index 7e1b0dfbb0..1dfd4c7ecd 100644
--- a/src/soc/intel/braswell/smbus.c
+++ b/src/soc/intel/braswell/smbus.c
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2017 Intel Corporation.
  * Copyright (C) 2019 3mdeb
+ * Copyright (C) 2019 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,6 +17,11 @@
 
 #include <device/early_smbus.h>
 #include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <device/pci_def.h>
+#include <device/pci_type.h>
+#include <device/pci_ops.h>
+#include <soc/smbus.h>
 #include <southbridge/intel/common/smbus.h>
 
 u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
@@ -27,3 +33,29 @@ u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
 {
 	return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value);
 }
+
+int smbus_i2c_block_write(u8 addr, u8 bytes, u8 *buf)
+{
+#ifdef __SIMPLE_DEVICE__
+	pci_devfn_t dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+#else
+	struct device *dev = pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
+#endif
+	u32 smbase;
+	u32 smb_ctrl_reg;
+	int status;
+
+	/* SMBus I/O BAR */
+	smbase = pci_read_config32(dev, PCI_BASE_ADDRESS_4) & 0xFFFFFFFE;
+
+	/* Enable I2C_EN bit in HOSTC register */
+	smb_ctrl_reg = pci_read_config32(dev, HOSTC);
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN);
+
+	status = do_i2c_block_write(smbase, addr, bytes, buf);
+
+	/* Restore I2C_EN bit */
+	pci_write_config32(dev, HOSTC, smb_ctrl_reg);
+
+	return status;
+}
-- 
cgit v1.2.3