From 1119428693e9a8b071115187e601f94d1d706c23 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Wed, 27 Mar 2019 10:39:55 +0100 Subject: soc/intel/braswell/smbus: Enable early SMBus in romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable early SMBus support compatible with SPD library using Intel SB common SMBus API. TEST=boot Protectli FW2B with new FSP, MemoryInit should pass without errors Signed-off-by: Michał Żygowski Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32062 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Patrick Georgi Reviewed-by: Nico Huber --- src/soc/intel/braswell/smbus.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/soc/intel/braswell/smbus.c (limited to 'src/soc/intel/braswell/smbus.c') diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c new file mode 100644 index 0000000000..7e1b0dfbb0 --- /dev/null +++ b/src/soc/intel/braswell/smbus.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); +} -- cgit v1.2.3