From e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 24 Sep 2015 12:26:31 -0500 Subject: intel fsp1_1: prepare for romstage vboot verification split In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/romstage/romstage.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'src/soc/intel/braswell/romstage') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 87b1af09df..0b1eab5f04 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -31,10 +31,6 @@ #include #include #include -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) -#include -#include -#endif #include #include #include @@ -170,7 +166,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) } /* SOC initialization before the console is enabled */ -void soc_pre_console_init(void) +void car_soc_pre_console_init(void) { /* Early chipset initialization */ program_base_addresses(); @@ -178,16 +174,12 @@ void soc_pre_console_init(void) } /* SOC initialization after console is enabled */ -void soc_romstage_init(struct romstage_params *params) +void car_soc_post_console_init(void) { /* Continue chipset initialization */ set_max_freq(); spi_init(); -#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) - /* Ensure the EC is in the right mode for recovery */ - google_chromeec_early_init(); -#endif lpc_init(); } -- cgit v1.2.3