From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/romstage/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/braswell/romstage') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 5fe3550509..e4180641a6 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -161,7 +161,7 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) if (ps->pm1_sts & WAK_STS) { switch (acpi_sleep_from_pm1(ps->pm1_cnt)) { case ACPI_S3: - if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) + if (CONFIG(HAVE_ACPI_RESUME)) prev_sleep_state = ACPI_S3; break; case ACPI_S5: @@ -229,7 +229,7 @@ void soc_memory_init_params(struct romstage_params *params, config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; -- cgit v1.2.3