From acb9c0b6616f96357c303964678eac05177a078d Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 2 Jul 2015 11:55:18 -0700 Subject: Braswell: Update to end of June. Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/intel/braswell/romstage/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/soc/intel/braswell/romstage') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index df6efd8bf2..64a3deee9a 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -187,6 +187,7 @@ void soc_romstage_init(struct romstage_params *params) /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); #endif + lpc_init(); } /* SOC initialization after RAM is enabled */ @@ -220,6 +221,7 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) params->PcdApertureSize = config->PcdApertureSize; params->PcdGttSize = config->PcdGttSize; params->PcdLegacySegDecode = config->PcdLegacySegDecode; + params->PcdDvfsEnable = config->PcdDvfsEnable; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -249,4 +251,6 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, old->PcdGttSize, new->PcdGttSize); soc_display_upd_value("PcdLegacySegDecode", 1, old->PcdLegacySegDecode, new->PcdLegacySegDecode); + soc_display_upd_value("PcdDvfsEnable", 1, + old->PcdDvfsEnable, new->PcdDvfsEnable); } -- cgit v1.2.3