From d077b58c61896c71218a90292bbcd5063c11698f Mon Sep 17 00:00:00 2001 From: Ravi Sarawadi Date: Wed, 9 Sep 2015 14:12:16 -0700 Subject: soc/braswell: Fix issues found during static code analysis TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/braswell/romstage/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/soc/intel/braswell/romstage/romstage.c') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 028469a2ca..5f2a1cefcf 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -200,6 +200,14 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", LPC_DEV, LPC_FUNC); + return; + } + config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? -- cgit v1.2.3