From 233ae1919b72434ca6cd783c9a946d32953bc7e9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 17:20:16 +0100 Subject: soc/intel/braswell: Clean up devicetree settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Frans Hendriks Reviewed-by: Michał Żygowski Reviewed-by: Furquan Shaikh --- src/soc/intel/braswell/romstage/romstage.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/soc/intel/braswell/romstage/romstage.c') diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index a82a4abc28..37ee93cd24 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -113,14 +113,14 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0; + upd->PcdMrcInitMmioSize = 0x800; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - upd->PcdApertureSize = config->PcdApertureSize; - upd->PcdGttSize = config->PcdGttSize; - upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdApertureSize = 2; + upd->PcdGttSize = 1; + upd->PcdLegacySegDecode = 0; upd->PcdDvfsEnable = config->PcdDvfsEnable; upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } -- cgit v1.2.3