From aee7ab2f6e69b70414f8225cb7a83c3e4cb62d9a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Mar 2020 00:31:58 +0100 Subject: soc/intel/braswell: Clean up Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected. Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/braswell/ramstage.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'src/soc/intel/braswell/ramstage.c') diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 9b0775e9b7..3e1625ff60 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -87,12 +87,15 @@ static void fill_in_pattrs(void) if (attrs->revid >= RID_D_STEPPING_START) { attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2; attrs->stepping += STEP_D1; + } else if (attrs->revid >= RID_C_STEPPING_START) { attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; attrs->stepping += STEP_C0; + } else if (attrs->revid >= RID_B_STEPPING_START) { attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; attrs->stepping += STEP_B0; + } else { attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; attrs->stepping += STEP_A0; @@ -114,15 +117,15 @@ static void fill_in_pattrs(void) /* Set IA core speed ratio and voltages */ fill_in_msr(&msr, MSR_IACORE_RATIOS); - attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_ratios[IACORE_MIN] = (msr.lo >> 0) & 0x7f; + attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ fill_in_msr(&msr, MSR_IACORE_VIDS); - attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; - attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_vids[IACORE_MIN] = (msr.lo >> 0) & 0x7f; + attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ -- cgit v1.2.3