From b19e33f05ca43a40babe4f081bf6fb0ff53f5d4f Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 15 Sep 2017 14:32:13 -0600
Subject: soc/intel/braswell: refactor rtc failure checking

In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.

BUG=b:63054105

Change-Id: Ic4bf99dc3a26fbc3bd508e484963b9298ef1b24b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/intel/braswell/pmutil.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

(limited to 'src/soc/intel/braswell/pmutil.c')

diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 018915c92b..4154522d4e 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <rules.h>
 #include <soc/iomap.h>
@@ -23,7 +24,7 @@
 #include <soc/pm.h>
 #include <stdint.h>
 
-#if ENV_SMM
+#if defined(__SIMPLE_DEVICE__)
 
 static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0);
 
@@ -354,3 +355,22 @@ void clear_pmc_status(void)
 	write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
 	write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts);
 }
+
+int rtc_failure(void)
+{
+	uint32_t gen_pmcon1;
+	int rtc_fail;
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+
+	if (ps != NULL)
+		gen_pmcon1 = ps->gen_pmcon1;
+	else
+		gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
+
+	rtc_fail = !!(gen_pmcon1 & RPS);
+
+	if (rtc_fail)
+		printk(BIOS_DEBUG, "RTC failure.\n");
+
+	return rtc_fail;
+}
-- 
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