From 32471729d9ebbabe809711ec55568925c6ce2070 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Mon, 20 Apr 2015 15:20:28 -0700 Subject: Braswell: Add Braswell SOC support Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy Reviewed-on: http://review.coreboot.org/10051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/braswell/northcluster.c | 89 ++++++++++++++++++++--------------- 1 file changed, 52 insertions(+), 37 deletions(-) (limited to 'src/soc/intel/braswell/northcluster.c') diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index af0fa5012b..d5d7268a8f 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,19 +18,24 @@ * Foundation, Inc. */ +#include +#include #include #include #include #include #include -#include - +#include +#include #include #include #include #include +#include +#include -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ BMBOUND_HI * | Usable DRAM | @@ -46,11 +52,13 @@ * +--------------------------+ SMMRRH, IRM0 * | TSEG | * +--------------------------+ SMMRRL + * | FSP Reserved Mem | + * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES * | Usable DRAM | * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resource model: + * coreboot's resrouce model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | @@ -64,7 +72,7 @@ * | Cacheable/Usable | * +--------------------------+ 0 */ -#define RES_IN_KiB(r) ((r) >> 10) +#define RES_IN_KIB(r) ((r) >> 10) uint32_t nc_read_top_of_low_memory(void) { @@ -74,10 +82,13 @@ uint32_t nc_read_top_of_low_memory(void) static void nc_read_resources(device_t dev) { unsigned long mmconf; - unsigned long bmbound; + unsigned long bmbound_k; unsigned long bmbound_hi; - unsigned long smmrrh; - unsigned long smmrrl; + void *smm_base; + size_t smm_size; + unsigned long tseg_base_k; + unsigned long tseg_top_k; + unsigned long fsp_res_base_k; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); int index = 0; @@ -85,60 +96,64 @@ static void nc_read_resources(device_t dev) /* Read standard PCI resources. */ pci_dev_read_resources(dev); + /* Determine TSEG data */ + smm_region(&smm_base, &smm_size); + tseg_base_k = RES_IN_KIB((unsigned long) smm_base); + tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); + + /* Determine the base of the FSP reserved memory */ + fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top()); + /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ - base_k = RES_IN_KiB(0); - size_k = RES_IN_KiB(0xa0000) - base_k; + base_k = RES_IN_KIB(0); + size_k = RES_IN_KIB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); - /* The SMMRR registers are 1MiB granularity with smmrrh being - * inclusive of the SMM region. */ - smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; - smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; - - /* 0xc0000 -> smrrl - cacheable and usable */ - base_k = RES_IN_KiB(0xc0000); - size_k = smmrrl - base_k; + /* 0xc0000 -> fsp_res_base - cacheable and usable */ + base_k = RES_IN_KIB(0xc0000); + size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); - if (smmrrh > smmrrl) - reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); + /* fsp_res_base -> tseg_top - Reserved */ + base_k = fsp_res_base_k; + size_k = tseg_top_k - base_k; + reserved_ram_resource(dev, index++, base_k, size_k); - /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); - mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + /* TSEG TOP -> bmbound is memory backed mmio. */ + bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); - /* The BMBOUND_HI register matches register bits of 31:24 with address - * bits of 35:28. Therefore, shift register to align properly. */ + /* + * The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. + */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); - bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; + bmbound_hi = RES_IN_KIB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + bmbound_hi - four_gig_kib); - /* Reserve everything between A segment and 1MB: + /* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10); chromeos_reserve_ram_oops(dev, index++); } static struct device_operations nc_ops = { - .read_resources = nc_read_resources, - .set_resources = NULL, - .enable_resources = NULL, - .init = NULL, - .enable = NULL, - .scan_bus = NULL, - .ops_pci = &soc_pci_ops, + .acpi_fill_ssdt_generator = generate_cpu_entries, + .read_resources = nc_read_resources, + .ops_pci = &soc_pci_ops, }; static const struct pci_driver nc_driver __pci_driver = { -- cgit v1.2.3