From f7c551cf6efe103688bb39563a7dca692431d766 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 7 Jul 2020 17:53:38 +0200 Subject: soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops. Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Wim Vervoorn --- src/soc/intel/braswell/lpss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/lpss.c') diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index d9027f5584..323d406d95 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), -- cgit v1.2.3