From 89739baf531e26dc81420df4f943bf8c163a0c0d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 25 Jul 2020 02:46:39 +0200 Subject: {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits We have definitions for the bits in the PCI COMMAND register. Use them. Also add spaces around bitwise operators, to comply with the code style. Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/braswell/lpss.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/lpss.c') diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index 7ff42c35df..961d405156 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -19,7 +19,8 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)), + REG_PCI_OR16(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), -- cgit v1.2.3