From cc5ac17fab97bd16f3122bb492fbdc28644c8567 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 30 Sep 2015 09:12:57 -0500 Subject: soc/intel/common: remove chipset specific calls The report_platform_info() and set_max_freq() are not being used similarly on skylake and braswell. With the addition of other SoCs I suspect a similar pattern will emerge. Instead of having weak functions to ensure things link with the hardcoded policy push these calls into their respective SoC homes. For parity, both skylake and braswell were updated to be consistent with the same calls prior to this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Built braswell. Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/303334 Original-Reviewed-by: Duncan Laurie Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/11815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/include/soc/romstage.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index a735c04db5..0f24f71c9f 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -33,6 +33,7 @@ void tco_disable(void); void punit_init(void); int early_spi_read_wpsr(u8 *sr); void mainboard_fill_spd_data(struct pei_data *pei_data); +void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -- cgit v1.2.3