From aff502e87ae57fa2dc09367d00f143b6befb9530 Mon Sep 17 00:00:00 2001 From: fdurairx Date: Fri, 21 Aug 2015 15:36:53 -0700 Subject: soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams Original-Reviewed-by: Aaron Durbin Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj Reviewed-on: https://review.coreboot.org/12732 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9e527e1b78..ec10101b5b 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) -- cgit v1.2.3