From 56d913eedb2f4f0df0b2210f139d857a829bdf96 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 4 Jun 2019 14:45:13 +0200 Subject: soc/intel/braswell: Use sb/intel/common/spi.c This common implementation is compatible. Change-Id: I540f73514f17d3b135c3222facfe23170d2bb0c8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/include/soc/spi.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index 2d275450fa..47de9da55b 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -22,14 +22,7 @@ /* These registers live behind SPI_BASE_ADDRESS. */ #define HSFSTS 0x04 -#define FDATA0 0x10 # define FLOCKDN (0x1 << 15) -#define SSFS 0x90 -# define CYCLE_DONE_STATUS (0x1 << 2) -# define FLASH_CYCLE_ERROR (0x1 << 3) -#define SSFC 0x91 -# define SPI_CYCLE_GO (0x1 << 1) -# define DATA_CYCLE (0x1 << 14) #define PREOP 0x94 #define OPTYPE 0x96 # define SPI_OPTYPE_RD_NOADDR 0x00 /* Read, no address */ -- cgit v1.2.3