From 540902ca47a9831d87761925b5df2699efc882a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jan 2021 08:02:50 +0200 Subject: intel/baytrail,braswell,broadwell: Add const qualifier for power_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- src/soc/intel/braswell/include/soc/romstage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/soc/intel/braswell/include') diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 2cf9afa633..3f38de8f2d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -11,7 +11,7 @@ void gfx_init(void); void punit_init(void); /* romstage.c functions */ -int chipset_prev_sleep_state(struct chipset_power_state *ps); +int chipset_prev_sleep_state(const struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ #define MEM_DDR3 0 -- cgit v1.2.3